chapter6-ex

1Chapter6ProblemSetChapter6PROBLEMS1.[E,None,4.2]ImplementtheequationX=((A+B)(C+D+E)+F)Gusingcomplemen-taryCMOS.SizethedevicessothattheoutputresistanceisthesameasthatofaninverterwithanNMOSW/L=2andPMOSW/L=6.Whichinputpattern(s)wouldgivetheworstandbestequivalentpull-uporpull-downresistance?2.ImplementthefollowingexpressioninafullstaticCMOSlogicfashionusingnomorethan10transistors:3.ConsiderthecircuitofFigure6.1.a.WhatisthelogicfunctionimplementedbytheCMOStransistornetwork?SizetheNMOSandPMOSdevicessothattheoutputresistanceisthesameasthatofaninverterwithanNMOSW/L=4andPMOSW/L=8.b.WhataretheinputpatternsthatgivetheworstcasetpHLandtpLH.Stateclearlywhataretheinitialinputpatternsandwhichinput(s)hastomakeatransitioninordertoachievethismaximumpropagationdelay.Considertheeffectofthecapacitancesattheinternalnodes.c.Verifypart(b)withSPICE.Assumealltransistorshaveminimumgatelength(0.25μm).d.IfP(A=1)=0.5,P(B=1)=0.2,P(C=1)=0.3andP(D=1)=1,determinethepowerdissipationinthelogicgate.AssumeVDD=2.5V,Cout=30fFandfclk=250MHz.4.[M,None,4.2]CMOSLogica.Dothefollowingtwocircuits(Figure6.2)implementthesamelogicfunction?Ifyes,whatisthatlogicfunction?Ifno,giveBooleanexpressionsforbothcircuits.b.Willthesetwocircuits’outputresistancesalwaysbeequaltoeachother?c.Willthesetwocircuits’riseandfalltimesalwaysbeequaltoeachother?Whyorwhynot?YAB⋅()ACE⋅⋅()DE⋅()DCB⋅⋅()+++=Figure6.1CMOScombinationallogicgate.ABVDDYCDCADB2Chapter6ProblemSet5.[E,None,4.2]Thetransistorsinthecircuitsoftheprecedingproblemhavebeensizedtogiveanoutputresistanceof13kΩfortheworst-caseinputpattern.Thisoutputresistancecanvary,however,ifotherpatternsareapplied.a.Whatinputpatterns(A–E)givethelowestoutputresistancewhentheoutputislow?Whatisthevalueofthatresistance?b.Whatinputpatterns(A–E)givethelowestoutputresistancewhentheoutputishigh?Whatisthevalueofthatresistance?6.[E,None,4.2]WhatisthelogicfunctionofcircuitsAandBinFigure6.3?Whichoneisadualnetworkandwhichoneisnot?Isthenondualnetworkstillavalidstaticlogicgate?Explain.Listanyadvantagesofoneconfigurationovertheother.7.[E,None,4.2]Computethefollowingforthepseudo-NMOSinvertershowninFigure6.4:a.VOLandVOHb.NMLandNMHc.Thepowerdissipation:(1)forVinlow,and(2)forVinhighd.Foranoutputloadof1pF,calculatetpLH,tpHL,andtp.Aretherisingandfallingdelaysequal?Whyorwhynot?8.[M,SPICE,4.2]ConsiderthecircuitofFigure6.5.VDDDA1FEB44464CBC6D6A6E6VDDDA1FEB44464CBC6D6A6E6CircuitACircuitBFigure6.2TwostaticCMOSgates.ABBABAABVDDFCircuitAABBABAABVDDFCircuitBFigure6.3Twologicfunctions.DigitalIntegratedCircuits-2ndEd3a.Whatistheoutputvoltageifonlyoneinputishigh?Ifallfourinputsarehigh?b.Whatistheaveragestaticpowerconsumptionif,atanytime,eachinputturnsonwithan(independent)probabilityof0.5?0.1?c.CompareyouranalyticallyobtainedresultstoaSPICEsimulation.9.[M,None,4.2]ImplementF=ABC+ACD(andF)inDCVSL.AssumeA,B,C,D,andtheircomplementsareavailableasinputs.Usetheminimumnumberoftransistors.10.[E,Layout,4.2]AcomplexlogicgateisshowninFigure6.6.a.WritetheBooleanequationsforoutputsFandG.Whatfunctiondoesthiscircuitimplement?b.Whatlogicfamilydoesthiscircuitbelongto?c.AssumingW/L=0.5u/0.25uforallnmostransistorsandW/L=2u/0.25uforthepmostran-sistors,producealayoutofthegateusingMagic.Yourlayoutshouldconformtothefol-lowingdatapathstyle:(1)Inputsshouldenterthelayoutfromtheleftinpolysilicon;(2)Theoutputsshouldexitthelayoutattherightinpolysilicon(sincetheoutputswouldprob-ablybedrivingtransistorgateinputsofthenextcelltotheright);(3)Powerandgroundlinesshouldrunverticallyinmetal1.d.Extractandnetlistthelayout.Loadbothoutputs(F,G)witha30fFcapacitanceandsimu-latethecircuit.Doesthegatefunctionproperly?Ifnot,explainwhyandresizethetransis-torssothatitdoes.Changethesizes(andareasandperimeters)intheHSPICEnetlist.VoutVinM1M22.5VPMOSNMOSFigure6.4Pseudo-NMOSinverter.W/L=4μm/0.25μmW/L=0.5μm/0.25μmABVDDFCDFigure6.5Pseudo-NMOSgate.(W/L)=1.5(W/L)=0.64Chapter6ProblemSet11.DesignandsimulateacircuitthatgeneratesanoptimaldifferentialsignalasshowninFigure6.7.Makesuretheriseandfalltimesareequal.12.WhatisthefunctionofthecircuitinFigure6.8?13.ImplementthefunctionS=ABC+ABC+ABC+ABC,whichgivesthesumoftwoinputswithacarrybit,usingNMOSpasstransistorlogic.DesignaDCVSLgatewhichimplementsthesamefunction.AssumeA,B,C,andtheircomplementsareavailableasinputs.14.DescribethelogicfunctioncomputedbythecircuitinFigure6.9.Notethatalltransistors(exceptforthemiddleinverters)areNMOS.SizeandsimulatethecircuitsothatitachievesaBBAAAFGVDDAFigure6.6Two-inputcomplexlogicgate.YYAAYY010101YY50%ofVDDFigure6.7DifferentialBuffer.YYABFigure6.8Gate.DigitalIntegratedCircuits-2ndEd5100psdelay(50-50)using0.25μmdevices,whiledrivinga100fFloadonbothdifferentialoutputs.(VDD=2.5V)AssumeA,Bandtheircomplementsareavailableasinputs.Forthedrainandsourceperimetersandareasyoucanusethefollowingapproxima-tions:AS=AD=W*0.625uandPS=PD=W+1.25u.15.[M,None.4.2]Figure6.10containsapass-gatelogicnetwork.a.Determinethetruthtableforthecircuit.Whatlogicfunctiondoesitimplement?b.Assuming0and2.5Vinputs,sizethePMOStransistortoachieveaVOL=0.3V.c.IfthePMOSwereremoved,wouldthecircuits