White-paper-Sofics-AdvCMOS40-28nm-ESD-approach

Whitepaper40/28nmESDapproachOn-chipESDprotectionclampsforadvanced40nmand28nmCMOStechnologyDespitetherisingcostforICdevelopment,EDAtoolsandmasksetssemiconductordesigncompaniescontinuetousethemostadvancedCMOStechnologyforhighperformanceapplicationsbecausebenefitslikelowerpowerdissipation,increasedgatedensity,higherspeedandlowermanufacturingcostperdiemorethancompensatethehighercost.Thisreturnoninvestmenthoweveronlypaysoffforultrahighvolumeapplications.Duetotheuseofsensitiveelements(suchasultrathin-oxidetransistors,ultra-shallowjunctions,narrowandthinmetallayers),increasedcomplexitythroughmultiplevoltagedomainsandtheuseofIPblocksfromvariousvendors,acomprehensiveESDprotectionstrategybecomesmoreimportant.Thiswhitepaperpresentson-chipESDprotectionclampsandapproachesfor40/28nmCMOSthatprovidecompetitiveadvantagebyimprovedyield,reducedsiliconfootprintandenableadvancedmultimediaandwirelessinterfaceslikeHDMI,USB3.0,SATA,WiFi,GPSandBluetooth.Thesolutionsarevalidatedintensofproductsrunninginfoundryandproprietaryfabricationplants.WhitePaper:Soficson-chipESDprotectionfor40nmand28nmCMOStechnologySoficsProprietary–©2011Page2IntroductionVarioussources[1-3]haveestimatedthetotaldevelopmentcostofacomplexSoCdesignin40nmsomewherebetween$30Mand$80M,dependingontheapplication.Duetotheshrinkingdesignrulesthelithographymasksgetmoreexpensiveateverynodenowuptoafewmilliondollarsat40nm.Further,alsothecostforEDAsoftwarecontinuestorisebecauseboththeSoCdesignsandtheprocessdesignconstraintsgetmorecomplexrequiringevermorepowerfulsoftware.Thisgrowingcomplexityisalsovisibleintherisinglaborcostsfordesign,layoutandtest.Figure1:SoCdevelopmentcostestimation,reachingmorethan$40Mat40nm–sourceInternationalBusinessStrategies&Altera.DespitethisrisingdevelopmentcostICdesigncompaniescontinuetousethemostadvancedCMOStechnologyforhighperformanceapplicationsbecausebenefitslikelowerpowerdissipation,increasedgatedensity,higherspeedandlowermanufacturingcostperdiemorethancompensatethehighercost.Figure2:RelativecostperfunctionisoneofthedrivingforcesbehindtheCMOStechnologyscaling.WhitePaper:Soficson-chipESDprotectionfor40nmand28nmCMOStechnologySoficsProprietary–©2011Page3Analystsbelieve[4]thatforICdesignsthereturnshouldbe10Xthedevelopmentcostwhichmeansthata40nmprojectshouldpresenta$300Mto$800Mmarketopportunity.Thisreturnoninvestmenthoweveronlypaysoffforultrahighvolumeapplications.Unfortunately,severalfactorscanstronglyreducethemarketshareandprofitmargins.Forinstanceinthenowdominantmarketofconsumerelectronics,theproductcyclesaremuchshorterandthepriceerosionstrongerthanafewyearsbackwhichmeansthattimetomarketisimportant.Ifyourproductislatebyafewmonthsacompetingproductcantakeoverandreduceyourpotentialsalesbyasmuchas30%duetoareducedmarketshareandreducedprofitmargin.TheanalystfirmInternationalBusinessStrategiesbelievesthata1yeardelaycouldwipeout91%ofthepotentialsalesvolume.Thelossofpotentialsalesvolumeisthemainreasonfor‘first-time-right’design,muchmoreimportantthanthecostsofdebuggingandre-spins.OnemajorfactorisoutofcontrolofICdesigners:theconsumerelectronicsbusinessisrapidlychanging.Onedayaproductishot,thenextdayitisoutdatedandnewfeaturesmustbeaddedtopleaseendcustomers.ICdesignersmustincorporateflexibilityforlatedesignchanges,includeprogrammabilityorcreateproductIC’sthatcancoveraclassofapplications.Anotherimportantfactoristheyieldoftheproductionandassembly.DFM(DesignforManufacturability)coversvarioustechniquestoimprovefunctionalyieldandreliabilityandisamustinadvancedCMOS.OnesuchreliabilityaspectisElectrostaticDischarge(ESD).Accordingtoexpertsitisresponsibleforatleast10%ofallproductfailuresinassembly.Duetotheuseofsensitivethin-oxidetransistors,increasedcomplexitythroughmultiplevoltagedomainsandtheuseofIPblocksfromvariousvendorsacomprehensiveESDprotectionstrategybecomesevermoreimportant.Thiswhitepaperpresentson-chipESDprotectionclampsandapproachesfor40nmCMOSthatprovidecompetitiveadvantagebyimprovedyield,reducedsiliconfootprintandenableadvancedmultimediaandwirelessinterfaceslikeHDMI,USB3.0,SATA,WiFi,GPSandBluetooth.Thesolutionsarevalidatedintensofproductsrunninginfoundryandproprietaryfabricationplants.ThepaperfirstdescribesthechallengesforESDprotectionin40nmand28nmCMOSfollowedbysomeESDrelevanttrendsandfinallyanoverviewofsiliconvalidatedclampsforcoreprotection,highspeedinterconnects,wirelessinterfaces,overvoltagetolerant(3V)IOs.WhitePaper:Soficson-chipESDprotectionfor40nmand28nmCMOStechnologySoficsProprietary–©2011Page4I.ESDChallengesfor40nmand28nmSoCsElectrostaticDischarge(ESD)isthesuddendischargeofachargedbodyanditisinevitableduringtheprocessingandassemblyofelectronicintegratedcircuits.WithouttheproperESDcontrolandon-chipESDprotectionitleadstofailuresintheIC’sjunctions,isolationoxidesormetallization.Toprotectthechip,ICdesignersincorporateso-calledclampdevicesatIOpads,powerpads(Vdd/Vss)andbetweenpowerdomains.TheESDdeviceshuntstheexcesscurrenttogroundandlimitstheon-chipvoltagedropbelowcriticallevels.Thefirstsubsectionbelowdescribeshowthiscriticalvoltagedrophasevolvedforadvance