2FSK调制解调系统的FPGA设计与实现

第38卷第3期2010年6月JOURNALOFZHEJIANGUNIVERSITYOFTECHNOLOGYVol.38No.3Jun.2010:20090915:(1966),,,,,,Email:[e-mail].2FSKFPGA,,(,310024):FSK(FrequencyShiftKeying)移频键控,或称数字频率调制,是数字通信中使用较早的一种调制方式.数字频率调制的基本原理是利用载波的频率变化来传递数字信息.在数字通信系统中,这种频率变化不是连续而是离散的.详细介绍了基于FPGA的2FSK调制解调系统的原理设计实现和调试,通过Quartus软件,在FPGA实验板上设计了一种全数字2FSK调制解调系统,并调试出结果.根据调试结果做出的优化设计,能够简化传统调制器的设计,缩短系统设计周期.:2FSK;FPGA;Quartus;HDL:TN914.3:A:10064303(2010)03028204Designandimplementationof2FSKmodulationdemodulationsystembasedonFPGAYINGYaping,XUJianfeng,CHENWangjun(ZhijiangCollege,ZhejiangUniversityofTechnology,Hangzhou310024,China)Abstract:FSKFrequencyShiftKeying,ordigitalfrequencymodulation,isanearliermodulationmodeusedindigitalcommunication.Thebasicprincipleofdigitalfrequencymodulationisusingthechangesofcarrierfrequencytotransmitdigitalinformation.Indigitalcommunicationsystems,thechangesoffrequencyarenotcontinuousbutdiscrete.Thepaperintroducestheprinciple,design,implementation,anddebugprocessofthe2FSKmodulationdemodulationsystembasedonFPGAindetails.UnderthesoftwareofQuartus,akindofdigital2FSKmodulationdemodulationsystemisdesignedontheFPGAexperiementalboardandthedebuggedresultsareachieved.Thedebuggedresultscanbeusedtooptimizethesystemdesign,simplifythedesignoftraditionalmodulatordemodulator,andshortentheperiodofsystemdesign.Keywords:2FSK;FPGA;Quartus;HDL,FPGA,.FPGA,.,.,,,.FSK,.[1].,,[2].FSK,,,FPGA.QuartusII,,2FSK,.12FSK1.12FSK2FSK,0,1,f10,f21.,2FSKf1f2,anan2ASK.2FSK:(1);(2)..,..,.2FSK,.,2FSK,.1.图12FSK键控信号的过零检测法解调原理框图Fig.1Thezeroassayof2FSK,,,,2.,,,.,,!1∀!0∀,[3].1.22FSK2FSK2.1f1,2f2,,,A/Df1f2.5m,.,2FSK.图22FSK调制解调系统图Fig.2Themodulationanddemodulationsystemdiagramof2FSKDADAC0832,,MX7821,.,,,.,.,dpll,.22FSKFPGA2.1m,(PN).PN,m,n(2n-1),.m.,.#283#3,:2FSKFPGAm5,mg(x)=x5+x2+1.D,3.XOR,OR5NOT.图3m序列电路图Fig.3msequencediagram2.2f1f2,.f1f2A/D,16.,f1_zb.vf2_zb.v,rom.vsin16.mif,rom.vQuartusIIMegaWizardPlugInManager.sin16.mif,simulink,workspace,QuartusIImif.matlabsin16.mif,:x=0:1:15;y=round(127*sin(2*pi*x/16))+128;A=[x;y];fid=fopen('C:\sin16.mif','w');fprintf(fid,'width=8;\r\ndepth=16;\r\n');fprintf(fid,'address_radix=dec;\r\ndata_radix=dec;\r\n');fprintf(fid,'contentbegin\r\n');fprintf(fid,'%d:%d;\r\n',A);fprintf(fid,'end;');fclose(fid);plot(x,y)plot16.2.3,,div8div16;m5m;muxm5,m,muxmf1f2,.32FSKFPGA3.1,A/Dmx7821;zx,;wf;pluse;lpf,.,,.,.3.2,,.FPGA,DPLL4.图4位同步原理图Fig.4Bitsynchronizationschematicdiagram,.N+1,N,N-1;...5.,,0~8(,),,,,.,.#284#38图5位同步锁相环算法图Fig.5Bitsynchronizationphaselockedloopalgorithm42FSK,,.6.moutm;zx;wf,wf;pulse,,,;bsyn;dout1.,dout1mout,.,.,FPGAEP1K30TC1443,A/DMAXIMMX7821,D/ADAC0832.QuartusIIAssignment/AssignmentEditor,QuartusIITools/Programmer,HardwareSetupByteBlaster,ModePassiveSerial,,.FPGA,moutdout1,6,.2FSK,.图6解调系统仿真图Fig.6Thewaveformofmodulationanddemodulationsystemsimulation5,A/D,,.,.FPGA,,.,,2FSK,2FSK.,,.:[1].(FSK)[J].,2009(9):3639.[2].[M].:,2001.[3],.FPGA[J].:,2005,29(2):2227.(:刘岩)#285#3,:2FSKFPGA