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APCPCWM_4828539:WP_0000005WP_0000005APCPCWM_4828539:WP_0000005WP_0000005Rev.1.2/Jul.20101204pinDDR3SDRAMSODIMM*HynixSemiconductorreservestherighttochangeproductsorspecificationswithoutnotice.DDR3SDRAMUnbufferedSODIMMsBasedon1GbT-dieHMT112S6TFR8CHMT125S6TFR8CB48614/178.104.2.80/2010-07-0811:46APCPCWM_4828539:WP_0000005WP_0000005APCPCWM_4828539:WP_0000005WP_0000005Rev.1.2/Jul.20102RevisionHistoryRevisionNo.HistoryDraftDateRemark0.1InitialReleaseSep.2009Preliminary1.0JEDECUpdateNov.2009Webposting1.1AddsupportedCL5Jun.2010Webposting1.2DIMMOutlineCorrectedJul.2010WebpostingB48614/178.104.2.80/2010-07-0811:46APCPCWM_4828539:WP_0000005WP_0000005APCPCWM_4828539:WP_0000005WP_0000005Rev.1.2/Jul.20103DescriptionHynixUnbufferedSmallOutlineDDR3SDRAMDIMMs(UnbufferedSmallOutlineDoubleDataRateSyn-chronousDRAMDualIn-LineMemoryModules)arelowpower,high-speedoperationmemorymodulesthatuseHynixDDR3SDRAMdevices.TheseUnbufferedDDR3SDRAMSODIMMsareintendedforuseasmainmemorywheninstalledinsystemssuchasmobilepersonalcomputers.Features*ThisproductisincompliancewiththeRoHSdirective.OrderingInformationPartNumberDensityOrganizationComponentComposition#ofranksHMT112S6TFR8C-G7/H91GB128Mx64128Mx8(H5TQ1G83TFR)*81HMT125S6TFR8C-G7/H92GB256Mx64128Mx8(H5TQ1G83TFR)*162•VDD=1.5V+/-0.075V•VDDQ=1.5V+/-0.075V•VDDSPD=3.0Vto3.6V•FunctionalityandoperationscomplywiththeDDR3SDRAMdatasheet•8internalbanks•Datatransferrates:PC3-10600,PC3-8500,orPC3-6400•Bi-directionalDifferentialDataStrobe•8bitpre-fetch•BurstLength(BL)switchon-the-fly:BL8orBC(BurstChop)4•OnDieTermination(ODT)supported•RoHScompliantB48614/178.104.2.80/2010-07-0811:46APCPCWM_4828539:WP_0000005WP_0000005APCPCWM_4828539:WP_0000005WP_0000005Rev.1.2/Jul.20104KeyParametersSpeedGradeAddressTableMT/sGradetCK(ns)CASLatency(tCK)tRCD(ns)tRP(ns)tRAS(ns)tRC(ns)CL-tRCD-tRPDDR3-1066-G71.875713.12513.12537.550.6257-7-7DDR3-1333-H91.5913.513.53649.59-9-9GradeFrequency[MHz]RemarkCL5CL6CL7CL8CL9CL10-G766780010661066-H966780010661066133313331GB(1Rx8)2GB(2Rx8)RefreshMethod8K/64ms8K/64msRowAddressA0-A13A0-A13ColumnAddressA0-A9A0-A9BankAddressBA0-BA2BA0-BA2PageSize1KB1KBB48614/178.104.2.80/2010-07-0811:46APCPCWM_4828539:WP_0000005WP_0000005APCPCWM_4828539:WP_0000005WP_0000005Rev.1.2/Jul.20105PinDescriptionsPinNameDescriptionNumberPinNameDescriptionNumberCK[1:0]ClockInput,positiveline2DQ[63:0]DataInput/Output64CK[1:0]ClockInput,negativeline2DM[7:0]DataMasks8CKE[1:0]ClockEnables2DQS[7:0]Datastrobes8RASRowAddressStrobe1DQS[7:0]Datastrobes,negativeline8CASColumnAddressStrobe1EVENTTemperatureeventpin1WEWriteEnable1TESTLogicAnalyzerspecifictestpin(NoconnectonSODIMM)1S[1:0]ChipSelects2RESETResetPin1A[9:0],A11,A[15:13]AddressInputs14VDDCoreandI/OPower18A10/APAddressInput/Autoprecharge1VSSGround52A12/BCAddressInput/Burstchop1BA[2:0]SDRAMBankAddresses3VREFDQInput/OutputReference1ODT[1:0]OnDieTerminationInputs2VREFCA1SCLSerialPresenceDetect(SPD)ClockInput1VTTTerminationVoltage2SDASPDDataInput/Output1VDDSPDSPDPower1SA[1:0]SPDAddressInputs2NCReservedforfutureuse2Total:204B48614/178.104.2.80/2010-07-0811:46APCPCWM_4828539:WP_0000005WP_0000005APCPCWM_4828539:WP_0000005WP_0000005Rev.1.2/Jul.20106Input/OutputFunctionalDescriptionsSymbolTypePolarityFunctionCK0/CK0CK1/CK1INCrossPointThesystemclockinputs.AlladdressandcommandlinesaresampledonthecrosspointoftherisingedgeofCKandfallingedgeofCK.ADelayLockedLoop(DLL)circuitisdrivenfromtheclockinputsandoutputtimingforreadoperationsissynchronizedtotheinputclock.CKE[1:0]INActiveHighActivatestheDDR3SDRAMCKsignalwhenhighanddeactivatestheCKsignalwhenlow.Bydeactivatingtheclocks,CKElowinitiatesthePowerDownmodeortheSelfRefreshmode.S[1:0]INActiveLowEnablestheassociatedDDR3SDRAMcommanddecoderwhenlowanddisablesthecommanddecoderwhenhigh.Whenthecommanddecoderisdisabled,newcommandsareignoredbutpreviousoperationscontinue.Rank0isselectedbyS0;Rank1isselectedbyS1.ODT[1:0]INActiveHighAssertson-dieterminationforDQ,DM,DQS,andDQSsignalsifenabledviatheDDR3SDRAMmoderegister.RAS,CAS,WEINActiveLowWhensampledatthecrosspointoftherisingedgeofCK,signalsCAS,RAS,andWEdefinetheoperationtobeexecutedbytheSDRAM.VREFDQVREFCASupplyReferencevoltageforSSTL15inputs.BA[2:0]IN—SelectswhichSDRAMinternalbankofeightisactivated.A[9:0],A10/AP,A11,A12/BCA[15:13]IN—DuringaBankActivatecommandcycle,definestherowaddresswhensampledatthecrosspointoftherisingedgeofCKandfallingedgeofCK.DuringaReadofWritecom-mandcycle,definesthecolumnaddresswhensampledatthecrosspointoftherisingedgeofCKandfallingedgeofCK.Inadditiontothecolumnaddress,APisusedtoinvokeautoprechargeoperationattheendoftheburstreadorwritecycle.IfAPishighautoprechargeisselectedandBA0-BAndefinesthebanktobeprecharged.IfAPislow,autoprechargeisdisabled.DuringaPrechargecommandcycle,APisusedinconjunctionwithBA0-BAntocontrolwhichbank(s)toprecharge.IfAPishigh,allbankswillbepre-chargedregardlessofthestateofBA0-BAninputs.IfAPislow,thenBA0-BAnareusedtodefinewhichbanktoprecharge.A12(BC)issamplesduringREADandWRITEcom-mandstodetermineifburstchop(on-the-fly)willbeperformed(HIGH,noburstchop:LOW,burstchopp