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Rev.1.2/Nov.20121204pinDDR3SDRAMSODIMM*SKhynixreservestherighttochangeproductsorspecificationswithoutnotice.DDR3SDRAMUnbufferedSODIMMsBasedon2GbE-dieHMT325S6EFR8CHMT351S6EFR8CRev.1.2/Nov.20122RevisionHistoryRevisionNo.HistoryDraftDateRemark0.1InitialReleaseMay.2012Preliminary1.0LatestJEDECSpecJun.20121.1JEDECSpecUpdatedAug.20121.2IDD5BspecmodifiedNov.2012Rev.1.2/Nov.20123DescriptionSKhynixUnbufferedSmallOutlineDDR3SDRAMDIMMs(UnbufferedSmallOutlineDoubleDataRateSyn-chronousDRAMDualIn-LineMemoryModules)arelowpower,high-speedoperationmemorymodulesthatuseDDR3SDRAMdevices.TheseUnbufferedDDR3SDRAMSODIMMsareintendedforuseasmainmemorywheninstalledinsystemssuchasmobilepersonalcomputers.Fetures•VDD=1.5V+/-0.075V•VDDQ=1.5V+/-0.075V•VDDSPD=3.0Vto3.6V•FunctionalityandoperationscomplywiththeDDR3SDRAMdatasheet•8internalbanks•Datatransferrates:PC3-14900,PC3-12800,PC3-10600•Bi-directionalDifferentialDataStrobe•8bitpre-fetch•BurstLength(BL)switchon-the-fly:BL8orBC(BurstChop)4•OnDieTermination(ODT)supported•ThisproductisinCompliancewiththeRoHSdirectiveOrderingInformationPartNumberDensityOrganizationComponentComposition#ofranksHMT325S6EFR8C-G7/H9/PB/RD2GB256Mx64256Mx8(H5TQ2G83EFR)*81HMT351S6EFR8C-G7/H9/PB/RD4GB512Mx64256Mx8(H5TQ2G83EFR)*162Rev.1.2/Nov.20124KeyParameters*SKhynixDRAMdevicessupportoptionaldownbinningtoCL11,CL9andCL7.SPDsettingisprogrammedtomatch.SpeedGradeAddressTableMT/sGradetCK(ns)CASLatency(tCK)tRCD(ns)tRP(ns)tRAS(ns)tRC(ns)CL-tRCD-tRPDDR3-1066-G71.875713.12513.12537.550.6257-7-7DDR3-1333-H91.5913.5(13.125)*13.5(13.125)*3649.5(49.125)*9-9-9DDR3-1600-PB1.251113.75(13.125)*13.75(13.125)*3548.75(48.125)*11-11-11DDR3-1866-RD1.071313.91(13.125)*13.91(13.125)*3447.91(47.125)*13-13-13GradeFrequency[MHz]RemarkCL5CL6CL7CL8CL9CL10CL11CL12CL13-G766780010661066-H96678001066106613331333-PB66780010661066133313331600-RD8001066106613331333160018662GB(1Rx8)4GB(2Rx8)RefreshMethod8K/64ms8K/64msRowAddressA0-A14A0-A14ColumnAddressA0-A9A0-A9BankAddressBA0-BA2BA0-BA2PageSize1KB1KBRev.1.2/Nov.20125PinDescriptionsPinNameDescriptionNumberPinNameDescriptionNumberCK[1:0]ClockInput,positiveline2DQ[63:0]DataInput/Output64CK[1:0]ClockInput,negativeline2DM[7:0]DataMasks8CKE[1:0]ClockEnables2DQS[7:0]Datastrobes8RASRowAddressStrobe1DQS[7:0]Datastrobes,negativeline8CASColumnAddressStrobe1EVENTTemperatureeventpin1WEWriteEnable1TESTLogicAnalyzerspecifictestpin(NoconnectonSODIMM)1S[1:0]ChipSelects2RESETResetPin1A[9:0],A11,A[15:13]AddressInputs14VDDCoreandI/OPower18A10/APAddressInput/Autoprecharge1VSSGround52A12/BCAddressInput/Burstchop1BA[2:0]SDRAMBankAddresses3VREFDQInput/OutputReference1ODT[1:0]OnDieTerminationInputs2VREFCA1SCLSerialPresenceDetect(SPD)ClockInput1VTTTerminationVoltage2SDASPDDataInput/Output1VDDSPDSPDPower1SA[1:0]SPDAddressInputs2NCReservedforfutureuse2Total:204Rev.1.2/Nov.20126Input/OutputFunctionalDescriptionsSymbolTypePolarityFunctionCK0/CK0CK1/CK1INCrossPointThesystemclockinputs.AlladdressandcommandlinesaresampledonthecrosspointoftherisingedgeofCKandfallingedgeofCK.ADelayLockedLoop(DLL)circuitisdrivenfromtheclockinputsandoutputtimingforreadoperationsissynchronizedtotheinputclock.CKE[1:0]INActiveHighActivatestheDDR3SDRAMCKsignalwhenhighanddeactivatestheCKsignalwhenlow.Bydeactivatingtheclocks,CKElowinitiatesthePowerDownmodeortheSelfRefreshmode.S[1:0]INActiveLowEnablestheassociatedDDR3SDRAMcommanddecoderwhenlowanddisablesthecommanddecoderwhenhigh.Whenthecommanddecoderisdisabled,newcommandsareignoredbutpreviousoperationscontinue.Rank0isselectedbyS0;Rank1isselectedbyS1.ODT[1:0]INActiveHighAssertson-dieterminationforDQ,DM,DQS,andDQSsignalsifenabledviatheDDR3SDRAMmoderegister.RAS,CAS,WEINActiveLowWhensampledatthecrosspointoftherisingedgeofCK,signalsCAS,RAS,andWEdefinetheoperationtobeexecutedbytheSDRAM.VREFDQVREFCASupplyReferencevoltageforSSTL15inputs.BA[2:0]IN—SelectswhichSDRAMinternalbankofeightisactivated.A[9:0],A10/AP,A11,A12/BCA[15:13]IN—DuringaBankActivatecommandcycle,definestherowaddresswhensampledatthecrosspointoftherisingedgeofCKandfallingedgeofCK.DuringaReadofWritecom-mandcycle,definesthecolumnaddresswhensampledatthecrosspointoftherisingedgeofCKandfallingedgeofCK.Inadditiontothecolumnaddress,APisusedtoinvokeautoprechargeoperationattheendoftheburstreadorwritecycle.IfAPishighautoprechargeisselectedandBA0-BAndefinesthebanktobeprecharged.IfAPislow,autoprechargeisdisabled.DuringaPrechargecommandcycle,APisusedinconjunctionwithBA0-BAntocontrolwhichbank(s)toprecharge.IfAPishigh,allbankswillbepre-chargedregardlessofthestateofBA0-BAninputs.IfAPislow,thenBA0-BAnareusedtodefinewhichbanktoprecharge.A12(BC)issamplesduringREADandWRITEcom-mandstodetermineifburstchop(on-the-fly)willbeperformed(HIGH,noburstchop:LOW,burstchopped).DQ[63:0]I/O—DataInput/Outputpins.DM[7:0]INActiveHighThedatawritemasks,associatedwithonedatabyte.InWritemode,DMoperatesasabytemaskbyallowinginputdatatobewrittenifitislowbutblocksthewriteoperationifitishigh.InReadmode,DMlineshavenoeffect.VDD,VDDSPDVSSSupplyPowersuppliesforcore,I/O,SerialPresenceDetect,andgroundforthemod