2016年度北邮数电实验报告

**数字电路与逻辑设计实验报告学院：电子工程学院班级：姓名：**学号：班内序号：**目录（一）实验名称及实验任务要求·························1（二）模块端口说明及连接图····························21.1实验三(3)模块端口说明····························21.2实验三(3)连接图···································22.1实验四模块端口说明·······························22.2实验四连接图······································2（三）原理图或VHDL代码································31.实验一(2)原理图·····································32.实验三(3)VHDL代码··································43.实验四VHDL代码····································7（四）仿真波形··············································101.实验一(2)仿真波形····································102.实验三(3)仿真波形····································113.实验四仿真波形·······································11（五）仿真波形分析··········································111.实验一(2)仿真波形分析································112.实验三(3)仿真波形分析································113.实验四仿真波形分析····································11（六）故障及问题分析·······································12（七）总结和结论············································13****（一）实验名称及实验任务要求实验一名称：QuartusII原理图输入法设计与实现实验任务要求：EDA基础实验1（1）、（2）、（3）必做，选做VHDL实现加法器。实验二名称：用VHDL设计与实现组合逻辑电路实验任务要求：四人表决器、8421码转格雷码、数码管译码器（下载测试）。实验三名称：用VHDL设计与实现时序逻辑电路实验任务要求：分频器、8421十进制计数器、将分频器/8421十进制计数器/数码管译码器3个电路进行连接并下载。实验四名称：用VHDL设计与实现相关电路实验任务要求：数码管动态扫描控制器、点阵扫描控制器。****（二）模块端口说明及连接图1.1实验三(3)模块端口说明cp：时钟信号输入；rst：8421十进制计数器异步置位；c[6...0]：七段二极管数码管显示；cat[7...0]：数码管显示。1.2实验三(3)连接图2.1实验四模块端口说明cp：时钟信号输入；rst：8421计数器异步复位；lgt[6...0]：七段二极管数码管显示；cat[7...0]：数码管显示。2.2实验四连接图**（三）原理图或VHDL代码1.实验一(2)原理图半加器：全加器：2.实验三(3)VHDL代码//分频器部分libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;**useieee.std_logic_arith.all;entitydiv_12isport(**cp:instd_logic;clk1:outstd_logic);enddiv_12;architectureaofdiv_12issignaltmp:integerrange0to11;beginprocess(cp)beginif(cp'eventandcp='1')theniftmp=11thentmp=0;elsetmp=tmp+1;endif;iftmp=5thenclk1='0';elseclk1='1';endif;endif;endprocess;enda;//8421十进制加法器部分**libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityjisuqi8421isport(clk2,rst:instd_logic;q:outstd_logic_vector(3downto0));endjisuqi8421;architectureaofjisuqi8421issignalq_temp:std_logic_vector(3downto0);beginprocess(clk2,rst)beginif(rst='1')thenq_temp=0000;**elsif(clk2'eventandclk2='1')thenifq_temp=1001thenq_temp=0000;elseq_temp=q_temp+1;endif;endif;endprocess;q=q_temp;enda;//译码管部分LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYyimaguanISPORT(a:INSTD_LOGIC_VECTOR(3downto0);b:OUTSTD_LOGIC_VECTOR(6downto0);cat:outstd_logic_vector(7downto0));endyimaguan;**ARCHITECTUREseg7_1_archOFyimaguanISBEGINPROCESS(a)BEGINCASEaISWHEN0000=b=1111110;--0WHEN0001=b=0110000;--1WHEN0010=b=1101101;--2WHEN0011=b=1111001;--3WHEN0100=b=0110011;--4WHEN0101=b=1011011;--5WHEN0110=b=1011111;--6WHEN0111=b=1110000;--7WHEN1000=b=1111111;--8WHEN1001=b=1111011;--9WHENOTHERS=b=0000000;ENDCASE;ENDPROCESS;cat=11101111;END;//整体显示**libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitydisplayisport(cp,rst:instd_logic;c:outstd_logic_vector(6downto0);cat:outstd_logic_vector(7downto0));enddisplay;architecturerofdisplayiscomponentdiv_12port(cp:instd_logic;clk1:outstd_logic);**endcomponent;componentjisuqi8421port(clk2,rst:instd_logic;q:outstd_logic_vector(3downto0));endcomponent;componentyimaguanport(a:instd_logic_vector(3downto0);b:outstd_logic_vector(6downto0);cat:outstd_logic_vector(7downto0));endcomponent;signalx:std_logic;signaly:std_logic_vector(3downto0);begin**u1:div_12portmap(cp=cp,clk1=x);u2:jisuqi8421portmap(clk2=x,rst=rst,q=y);u3:yimaguanportmap(a=y,b=c,cat=cat);endr;3.实验四VHDL代码//分频器分频部分libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entitydivisport(cp:instd_logic;clk1:outstd_logic);enddiv;architectureaofdivissignaltmp:integerrange0to49;**beginprocess(cp)beginif(cp'eventandcp='1')theniftmp=49thentmp=0;elsetmp=tmp+1;endif;iftmp=25thenclk1='0';elseclk1='1';endif;endif;endprocess;enda;//计数器计数部分libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;**entitycountisport(clk,rst:instd_logic;q:outstd_logic_vector(3downto0));endcount;architectureaofcountissignaltemp:std_logic_vector(3downto0);beginprocess(clk,rst)beginif(rst='1')thentemp=0000;elsif(clk'eventandclk='1')theniftemp=0101thentemp=0000;elsetemp=temp+1;**endif;endif;endprocess;q=temp;enda;//译码管显示部分libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityyimaqiisport(a:instd_logic_vector(3downto0);led:outstd_logic_vector(6downto0);cat:outstd_logic_vector(7downto0));endentity;architecturertlofyimaqiisbegin**process(a)begincaseaiswhen0000=led=1111110;cat=11111110;--0when0001=led=0110000;cat=11111101;--1when0010=led=1101101;cat=11111011;--2when0011=led=1111001;cat=11110111;--3when0100=led=0110011;cat=11101111;--4when0101=led=1011011;cat=11011111;--5whenothers=led