快速建立时间的自适应锁相环AnAdaptivePLLA

296Vol.29No.620076JournalofElectronics&InformationTechnologyJun..2007(100084)(508055)()()()SMIC0.18µm1.8VCMOSSpectre0.1%30%TN763.2A1009-5896(2007)06-1492-04AnAdaptivePLLArchitecturetoAchieveFastSettlingTimeHuangShui-longWangZhi-hua(DepartmentofElectronics,TsinghuaUniversity,Beijing100084,China)(ShenzhenGraduateSchool,TsinghuaUniversity,Shenzhen518055,China)Abstract:Therelationshipsbetweenloopperformance(settlingtime,phasenoiseandspursignal)andloopparameters(bandwidthandphasemargin)arebrieflydiscussedinthepaper.AnadaptivePhase-LockedLoop(PLL)withafastsettlingtimeanditskeyblocksincludingPhase-FrequencyDetector(PFD)andchargepumparethenproposedandanalyzed.Theproposedarchitectureisbasedontwotuningloops:acoarse-tuningloopandafine-tuningloop.Thecoarse-tuningloopisusedforfastconvergenceandthefine-tuningloopisusedtocompletefineadjustments.Adaptationofloopparametersoccurscontinuously,withoutswitchingofloopfiltercomponents,andwithoutinteractionfromoutsidecontrolsignal.SpectresimulationbasedonSMIC0.18µm1.8VsupplyvoltageCMOStechnologyshowsthatcoarse-tuningPFDcaneffectivelycutoffcoarse-tuningloop,andthechargepumphasa0.1%up/downcurrentmismatchingcharacteristic.TheadaptivePLLcanreducesettlingtimeover30%incomparisontotheconventionalPLLinthesameloopbandwidth.Keywords:PLL;PFD;Chargepump1(PLL)PLL2005-11-282006-05-31(60475018)(G2000036508)(PFD)[1][2]23456251493VCO50°[3,4]32PLL11PLLfref121VCO1R2C3PLLfreffdivΦeΦePFDΦd||feQIΦ=×PFDΦd||(||||)fecedQIIΦΦΦ=×+−If2Ic1PLLωc(1)chVCO12cIKRNωπ××≈×(1)IchKVCONωcIchΦePFDΦd(1)ΦePFDΦdIfPLL4[5]23(a)23149429A1B1QAB1B1A1QBA12delay223ns[1]3(b)A1B1tA1B1delay2tdA1B1delay2tdPFDPFDVCOA1B1delay2tdQAQB2QAPMOS5PLL[6],124[7]PLLMC1MC24(a)VREFVOUT4M8=M1,M11=M7,M10=M9,M12=M3UP0DN0I1I2I3UP1DN1I1I2I4VOUTPLLen1M9M9MS1MS2MS3OUTOUTREFMS2MS3M10M9OUTREFMS2MS2MS2MOSM9M3M3M1OUTOUT61fref19.2MHzVCO1.87GHz–1.94GHzCP11.2mACP2200µAC1=830pFC2=28pFR15.2kR24kC350pF1003.5nsverilogA0.18µm1.8VSMICCMOSSpectre550D106kHz460kHz48D4.56PLL13µsPLL9µs78µsPLL8201.2V55149567820.1%7()PLLPLL30%PLL[1]CiceroSV.AnadaptivePLLtuningsystemarhitectureCombininghighspectralpurityandfastsettlingtime[J].IEEEJ.Solid-StateCircuits,2000,35(4):490–502.[2]ChengKuo-HsingandYangWei-Bin.Adual-slopephasefrequencydetectorandchargepumparchitecturetoachievefastlockingofphase-lockedloop.IEEECAS-II,2003,50(11):892–896.[3]HanumoluPK,BrownleeM,andMoonUn-Ku.Analysisofcharge-pumpphase-lockloops[J].IEEETrans.onCircuitsandSystemsI,2004,51(9):1665–1674.[4]VauncherCandKasperkovitzD.Awide-bandtuningsystemforfullyintegratedsatellitereceivers[J].IEEEJ.Solid-StateCircuits,1998,33(7):987–998.[5]LeeJoonsukandKimBeomsup.Alow-noisefast-lockphase-lockedloopwithadaptivebandwidthcontrol[J].IEEEJ.Solid-StateCircuits,2000,35(8):1137–1145.[6],,.N[J].,2004,44(7):958–961.WuEn-de,WangZhi-hua,andZhangLi,etal..Spuranalysisoffractional-Nfrequencysynthesizers[J].JTsinghuaUniv(Sci&Tech),2004,44(7):958–961.[7]LeeJae-Shin,KeelMin-Sun,LimShin-II,andKimSuki.Chargepumpwithperfectcurrentmatchingcharacteristicsinphase-lockedloops[J].ElectronicsLetters,2000,36(23):1907–1908.1975.1960.