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ConfidentialBU5-SYSRD1-CoreTechnologyDept.2(PowerDept.)BoardPowerLayoutNoteMB/VGA/Server/NBPowerlayout(佈局與佈線)noticeBU5-SYSRD1-CoreTechnologyDept.2(PowerDept.)ConfidentialOutline•Placement–Overview:POLexampleofMB,Server,NBandVGA.–PowerStage:I/PCap,O/PCap,Sunbber,MOSFETplacementnotice–Controller:shortpinand外圍元件placement.–Driver:locationand外圍元件placement.•PartitionLayers–Overview:PCBStack-Upexample–Phase/Vcc/GND:PartitionofPhase/Vcc/GND•TraceandPartition–TracewidthandGroupdistance–Noisesourceandsensitivecircuit–Tracelayoutguide•Others:–Via,TracedropcalculationBU5-SYSRD1-CoreTechnologyDept.2(PowerDept.)ConfidentialPlacement-OverviewBU5-SYSRD1-CoreTechnologyDept.2(PowerDept.)ConfidentialPlacement-Overview•POL(PointofLoad)是PowerStage元件擺放的原則.•PowerStage是指(又見下兩圖):–較大的電源分怖環路中的元件.如:BulkCap,MOSFET,OutputInductor,PWMIC,…–去耦合環路的元件.如:MLCC,Bead,..IOCPUSocketNBSBPCIPCIEDIMMUSBUSB–VcoreswforCPU–+1p2VCLforNB–+1p8Vswand+0p9VforDIMM–+1p05VforSB–+1p2VcoreswforNB–+3p3VSBforSBandLAN–+5V_DualforUSBand1p8VswIntelMB:SATA24pinsandIDEGND+1.25V+1.05V_ICHGND+1.05V_ICH_REF+1.05V_ICH_CON+1.05V_ICH_FBLM324_VCCPC?470PF/50VI12GSD321PQ17AP9T15GHIPRN2B1KOhmI34VCCGNDPU4BLM324DRI765411+PCE15820UF/6.3VI12LANILOWERPWMIUPPERILOIOUTVPHASEVOUTVINBU5-SYSRD1-CoreTechnologyDept.2(PowerDept.)ConfidentialPlacement-OverviewIOCPUSocketNB+SBPCIPCIEDIMMUSBUSB–VcoreswandVDDNBswforCPU–+1p2VHTforCPU,NB+SB–+1p8Vand+0p9VforDIMM–+2p5VforCPU–+1p1VswforNB+SB–+3p3VSBand+1p1VSBforNB+SBandLAN–+5V_DualforUSBand1p8VswAMDMB:SATA24pinsandIDELANCPUSocketNBPowerInBladeServer:SBDIMMIO–+VcoreswforCPU–+1p05VswforNB–+1p25VMforNB–+1p25VforNB–+1p05VMforNB–+1p5VforSB–+1p8V_DualswforDIMM–+VTTDDRfroDIMMBU5-SYSRD1-CoreTechnologyDept.2(PowerDept.)ConfidentialPlacement-OverviewVGA(ATX):CPUBotSocketNBBotNB:SBTopDIMMBotChargerPowerINNBvoltagerailnotes:–V-DualPower–Vs-MainPower–Vsus-VSBHDMITVDVIDDRDDRGPUHeat-Sink–VcoreforCPU–+1p8VforDIMM&NB–+VTTDDRforDIMM–Charger–+12Vs–+1p5VsforNB&SB–+1p05VsforNB&SB&CPU–+5VforUSB,Camera+5VSforODD,HDD,Codec+3VSforMiniCard,HDD,BT+3VsusforLAN,MDCandMiniCardTVDVIDDRGPUHeat-SinkVGA(LowProfile):–+2p5VforI/O–+NVVDD/VDDCswforGPU–+1p1VforGPU–+5VforI/O–FBVDDQ/MVDDswforDDR(orGPU/AMD)Note:nVIDIA/AMDBU5-SYSRD1-CoreTechnologyDept.2(PowerDept.)ConfidentialPlacement-OverviewServer:PowerINDIMM-1DIMM-2CPU-1CPU-0PCIBMCPCI8NBSBLANLANIOPCIPCI8–+Vcore0/2swforCPU-0/1–CPU0/1_+1p1VswforCPU-0/1–CPU0/1_+1p5VswforCPU-0/1–-+0p75V_CPU0/1forCPU-0/1–+3VswforAccessories–+5VswforAccessories–+3VAUX–3VSBswforBMC,PCI–+1p2VAUX_BMC–+1p8VAUX–IoH_+1p8VSB–IoH_+0p9VSB–IoH_+1p1Vsw–IoH_+1p1VAUX–LAN_+1VAUX–ICH_+1p5V–ICH_+1p05VBU5-SYSRD1-CoreTechnologyDept.2(PowerDept.)ConfidentialPlacement-PowerStage:ConnectorBU5-SYSRD1-CoreTechnologyDept.2(PowerDept.)ConfidentialPlacement-PowerStage:Connector•現象:Connector的防呆端離立式電感太近!•原因:插拔powersupply時，會卡到電感。•改進措施:將Connector調轉，使防呆端遠離立式電感。•Summary:Connector的防呆端不要朝向DIP電容和立式電感，防止卡機構。BU5-SYSRD1-CoreTechnologyDept.2(PowerDept.)ConfidentialPlacement-PowerStage:輸入電容（ELCAP和MLCC）BU5-SYSRD1-CoreTechnologyDept.2(PowerDept.)ConfidentialPlacement-PowerStage:輸入電容（ELCAP和MLCC）•現象:輸入電容離H/SMOSFET太近!•原因:由於MOSFET的溫度較高，如果離輸入電容太近，其熱量可能傳到電容上，從而縮短電容的壽命。•改進措施:在條件允許（有空間且沒有走綫）的情況下，盡量將電容移開，離H/SMOSFET稍遠，且均勻擺放。InputcapInputcapBU5-SYSRD1-CoreTechnologyDept.2(PowerDept.)ConfidentialPlacement-PowerStage:輸入電容（ELCAP和MLCC）•現象:輸入電容離輸入電感太遠!•原因:在H/SMOSFET打開的瞬間，可能不能及時從輸入電容抽取電流，從而將L+12V拉低，導致輸入不穩定或UVLO。•改進措施:將輸入電容放到靠近輸入電感処。InputchokeInputcapInputchokeInputcapBU5-SYSRD1-CoreTechnologyDept.2(PowerDept.)ConfidentialPlacement-PowerStage:輸入電容（ELCAP和MLCC）•現象:輸入MLCC沒放到H/SMOSFET的Drainpin旁!•原因:離H/SMOSFET太遠不能有效濾除MOSFETDrain端因開關引起的spike，可能超過MOSFET的breakdownVoltage，燒掉H/SMOSFET且O/PRipple會被Inducespike影響。•改進措施:將輸入MLCC放到H/SMOSFET的Drainpin旁。HSI/PMLCCHSI/PMLCCBU5-SYSRD1-CoreTechnologyDept.2(PowerDept.)ConfidentialPlacement-PowerStage:輸入電容（ELCAP和MLCC）•Summary:對於輸入電容的placement應注意以下幾點,–輸入電容要放在輸入電感的后端且盡量均勻的擺放在每一相，起到及時補充電流的作用;–為延長ELCAP和OS-CON的壽命，在條件允許的情況下，應使其遠離熱源H/SMOSFET;–輸入的MLCC必須均勻摆放在每一相H/SMOSFET的DrainPin旁邊，來濾除L+12V的雜訊,降低spike以及O/PRippleVoltage。–I/PCap需注意限高，尤其是DIMMlatch以及PCIE部分。BU5-SYSRD1-CoreTechnologyDept.2(PowerDept.)ConfidentialPlacement-PowerStage:MOSFET,Snubber&ChokeBU5-SYSRD1-CoreTechnologyDept.2(PowerDept.)ConfidentialPlacement-PowerStage:MOSFET,Snubber&Choke•現象:L/SMOSFET擺放不合理!•原因:layout在鋪phase的shape時可能出現瓶頸，導致電流不均勻分攤於兩顆MOSFET。•改進措施:將MOSFET換個方向擺放，使其在layout時不會出現瓶頸。•Note:Power建議20~40milshape流1A電流，但尚需考慮Thermal,VoltageDrop。H/SOutputChokeL/SH/SO/PChokeL/SBU5-SYSRD1-CoreTechnologyDept.2(PowerDept.)ConfidentialPlacement-PowerStage:MOSFET,Snubber&Choke•現象:L/SMOSFETGate電阻離L/SMOSFET太遠!•原因:gate電阻應靠近MOSFETgate端擺放。•改進措施:將Gate電阻放到MOSFET的Gatepin旁邊。L/SRgDriverL/SRgBU5-SYSRD1-CoreTechnologyDept.2(PowerDept.)ConfidentialPlacement-PowerStage:MOSFET,Snubber&Choke•現象:Phase破層!•原因:Phaseshape不完整不利于散熱，可能導致這塊shape的thermal過高。•改進措施:將Snubber電容向下移，保證phaseshape的完整性。SnubberSnubberBU5-SYSRD1-CoreTechnologyDept.2(PowerDept.)ConfidentialPlacement-PowerStage:MOSFET,Snubber&Choke•現象:snubber擺放位置不正確!•原因:對phasenode的spike吸收效果不好，導致spike過高，超過MOSFET的breakdownVolta