四道光罩技术简介

IntroductiontoTechnologyof4-PEPsArrayDesignTeamWhy4-PEPs◎CostDown1.Reductionofphotolithography(1/5).2.Reductionofinvestmentinexpensiveexposuremachine.3.Moreeasytocontrolmaskusing.4.Reducingcostofphotomask(~10%).◎AdvancedTechnologyDevelopment1.Cstincreasinganddisplayqualitypromotion.2.Pixelapertureratioincreasing.3.Wideviewandtransflectivetechnology?WhatIs4-PEPsGE/WetSE&SDSlitPhotoSD(Channel)/WetSE/DryP.R./DrySD/WetSE(BCE)/DryPassivation/DryPE/WetM3M4M2M1GE/WetSE/DrySD/WetM1M2M3SE(BCE)/DryPassivation/DryPE/WetM4M54-PEPsProcessStep-1.GateElectrode1stPhotoMaskGlassSubstrateGateElectrodeGateInsulator4-PEPsProcessStep-2.GateInsulatorDepositionGlassSubstrateGateElectrodea-SiLayer4-PEPsProcessStep-3.a-SiLayerDepositionGateInsulatorGlassSubstrateGateElectrode4-PEPsProcessStep-4.Source&DrainLayerDepositiona-SiLayerGateInsulatorGlassSubstrateGateElectrodeSDLayer4-PEPsProcessStep-5.PhotoResistSpinCoatinga-SiLayerGateInsulatorGlassSubstrateGateElectrodeSDLayerPhotoResist4-PEPsProcessStep-6.Half-TonePhotolithography2ndPhotoMaska-SiLayerGateInsulatorGlassSubstrateGateElectrodeSDLayerPhotoResist4-PEPsProcessStep-7.SDWetEtchinga-SiLayerGateInsulatorGlassSubstrateGateElectrodeSDLayerPhotoResist4-PEPsProcessStep-8.SEDryEtchingGateInsulatorGlassSubstrateGateElectrodea-SiLayerSDLayerPhotoResist4-PEPsProcessStep-9.Ashing/DryEtchingGateInsulatorGlassSubstrateGateElectrodea-SiLayerSDLayerPhotoResist4-PEPsProcessStep-10.ChannelSDWetEtchingGateInsulatorGlassSubstrateGateElectrodea-SiLayerSDLayerPhotoResist4-PEPsProcessStep-11.BCEDryEtchingGateInsulatorGlassSubstrateGateElectrodea-SiLayerSDLayerPhotoResist4-PEPsProcessStep-12.PhotoResistRemote/AshingGateInsulatorGlassSubstrateGateElectrodea-SiLayerSDLayerPassivation4-PEPsProcessStep-13.PassivationGateInsulatorGlassSubstrateGateElectrodea-SiLayerSDLayer4-PEPsProcessStep-14.ContactHole3rdPhotoMaskPassivationGateInsulatorGlassSubstrateGateElectrodea-SiLayerSDLayer4-PEPsProcessStep-15.ITOElectrode4thPhotoMaskPassivationGateInsulatorGlassSubstrateGateElectrodea-SiLayerSDLayer5-PEPsProcessStep-1.GateElectrode1stPhotoMaskGlassSubstrateGateElectrodeGateInsulator5-PEPsProcessStep-2.GateInsulatorDepositionGlassSubstrateGateElectrodea-SiLayer5-PEPsProcessStep-3.a-SiLayerDepositionGateInsulatorGlassSubstrateGateElectrode5-PEPsProcessStep-4.SEDryEtching2ndPhotoMaskGateInsulatorGlassSubstrateGateElectrodea-SiLayerSDLayer5-PEPsProcessStep-5.Source&DrainLayerDepositionGateInsulatorGlassSubstrateGateElectrodea-SiLayer5-PEPsProcessStep-6.SDWetEtching3rdPhotoMaskGateInsulatorGlassSubstrateGateElectrodea-SiLayerSDLayer5-PEPsProcessStep-7.BCEDryEtchingGateInsulatorGlassSubstrateGateElectrodeSDLayera-SiLayer5-PEPsProcessStep-8.PassivationGateInsulatorGlassSubstrateGateElectrodeSDLayera-SiLayerPassivationPassivation5-PEPsProcessStep-9.ContactHole4thPhotoMaskGateInsulatorGlassSubstrateGateElectrodeSDLayera-SiLayerPassivation5-PEPsProcessStep-10.ITOElectrode5thPhotoMaskGateInsulatorGlassSubstrateGateElectrodeSDLayera-SiLayerGray-Tone-MaskHalf-Tone-MaskGTM&HTMAdvantage◎MPstageDisadvantage◎LargeareahalftoneisimpossibleAfewvarietyofapplication◎CD,PRprofileismuchsensitiveagainstMaskCDvariationFewerprocessmarginAdvantage◎LargeareahalftoneispossibleWidevarietyofapplication◎BetterPRprofile,fewTr.(H.F.)variationProspectWideprocessmarginDisadvantage◎DevelopmentstageDiffractioneffectbyusingfine(beyondresolution)patternonmask.Transmittancecontrolbyadditionalhalftonefilmonmask.GTM&HTM◎PessimistictoG6andnextGen.◎DifficulttocontrolfineslitFewerprocessmargin◎Strongerexposureenergyisneeded.Longertacttime◎PotentialforG6andnextGen.Widevarietyofapplication◎GoodPRuniformity◎WideprocessmarginFineslitGray-Tone-MaskHalf-Tone-MaskHalffilmGray-ToneMask(GTM)DataFrom:LGMGray-ToneMask(GTM)DataFrom:HOYAHalf-ToneMask(HTM)DataFrom:HOYAHalf-ToneMask(HTM)DataFrom:HOYAHalf-ToneMask(HTM)VersionTFTCADOpticalSimulationDNP6-inchHTMReticle1stEditionDNP6-inchHTMReticle2ndEditionApplicationof4-PEPs◎液晶顯示裝置--以Half-Tone光罩增加Array電氣特性的方法◎液晶顯示裝置--四道黃光製程之元件設計◎液晶顯示裝置--改良OCB色偏◎液晶顯示裝置--IPS配向顯示異常設計T1(GP)L7by4-PEPsCommitment．Partnership．TechnologyThankYou