前瞻网路安全处理器及相关SOC设计与测试技术研发

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DesignTechnologyCenterNationalTsingHuaUniversityNetworkSecurityProcessorandtheRelatedSOCDesignandTestTechnologiesBistforRAmINSecondsJuly,2006前瞻網路安全處理器及相關SOC設計與測試技術研發2MemoryTestingProblem&SolutionsProblem:memorymanufacturingisnotperfectNeedtesting,diagnosis,andrepairRAMSES:RAM/FlashfaultsimulatorTAGS:RAM/Flashtestalgorithm(pattern)generatorBRAINS:RAMBISTgeneratorFAME:memoryfailureanalyzerDesign(Layout)DefectInjectionFaultyCellBehaviorFaultModelsFaultModelsTestAlgorithmsBuilt-InSelf-TestBuilt-InSelf-RepairTester前瞻網路安全處理器及相關SOC設計與測試技術研發3MemoryBISTAutomationFlowBRAINS:BISTforRAMsinSecondsBISTIntermediateDescriptionSimulation/Synthesis/P&RFlowBRAINSgbrainsMemoryLibraryBISTTemplatesBIDConstructorCompilerKernelBISTDesignActivationSequencesIntegrationScriptsMemorySpecTestRequirementMemoryCompilerIPGeneratorsCommandScriptsGUI前瞻網路安全處理器及相關SOC設計與測試技術研發4TestScheduleandTestGroupingSingle-portSRAMGroup0ControllerSequencer1Dual-portSRAMGroup12R1WRegisterFileSingle-portSRAMReadportWriteportRead-writeportSequencer0Group0Parameters:MemorytypeMemoryspec.PowerconstraintUserdefine前瞻網路安全處理器及相關SOC設計與測試技術研發5AlgorithmProgramming&TestScheduling前瞻網路安全處理器及相關SOC設計與測試技術研發6DrivingCapability&PipelineOptimization前瞻網路安全處理器及相關SOC設計與測試技術研發7BISTCircuitGenerationFlowMemoryInfo.TestAlgorithmTestSchedulingDriving/TimingSpec.BISTCompileStartRTL,TB,Syn.ScriptMemorymodel,address,wordwidthDefault/ProgrammableAuto/UserdefinedPinloading,latencyBID前瞻網路安全處理器及相關SOC設計與測試技術研發8BISTArchitectureMemoryBISTExternalTesterMBSMSIMBOMRDMSOMBCMBRMCKControllerRAMRAMRAMRAMRAMRAMSequencerSequencerSequencerTPGTPGTPGTPGTPGTPG前瞻網路安全處理器及相關SOC設計與測試技術研發9ExperimentResult&ComparisonMemorySpec:64X64:2modules64X128:3modules512X64:1module512X128:2modulesFullspeedtesting--clockrate:100MHzDiagnosisfunctionTestalgorithm:MarchC-(Mentor),MarchCW(BRAINS)Testtime(cycle)GatecountBRAINS2,423,50028,910Mentor20,080,90030,353前瞻網路安全處理器及相關SOC設計與測試技術研發10FAMEFAME:FailureAnalyzerforMemoriesMECA:MemoryErrorCatcherandAnalyzerRAMSES:RAMfaultsimulatorTAGS:RAMtestalgorithmgeneratorERA:RAMerroranalyzerMDD:MemoryDefectDiagnosisToolAFA:AutomaticFaultAnalyzerFPA:Failure/FaultPatternAnalyzerGUI-basedFailure/FaultPatternViewer前瞻網路安全處理器及相關SOC設計與測試技術研發11FAME:FailureAnalyzerforMemory前瞻網路安全處理器及相關SOC設計與測試技術研發12RealisticDefectInjectionPurpose:todetermineifacircuitisdamagedbyacertaindefectOpenDefectsShortDefectsDContact/ViaMissingContactD前瞻網路安全處理器及相關SOC設計與測試技術研發13DiagnosticsUsingFaultPatternsAcause-effectapproach:FaultPatternsDefectiveNetlistRealisticFaultPatternsPredictionStageApplicationStageSimulationReductionDefectDictionaryDefectCandidates前瞻網路安全處理器及相關SOC設計與測試技術研發14FaultPatternAnalysisResults:SAF1:RDF(1):Unmodeld:SAF0:CFid(U;1)FP5FP3FP3FP5FP1FP6FP1FP1FP2FP3FP3FP3FP5FP5FP3FP5FP5orFP5+FP3FP5+FP5FP5orFP5+FP3FP5+FP5前瞻網路安全處理器及相關SOC設計與測試技術研發15GenerationDefectDictionarySimulationCircuit-levelGenerationFaultPatternRealisticDefectFailure/FaultFaultBitmapInjectionFaultPatternsMemSpec.SimulationResultsArch.DistributionDefectDictionaryDefectScramblingTestConditionProcessFault/FailurePatternClassificationDefectCandidatesFailureStatisticsInspectionIn-lineTestAlgorithmVoltage,SpeedFaultyCircuitPatternAnalyzerAutomaticInductiveFaultAnalysisSizeConductivityDesignLayoutNetlistMarchDictionaryMemoryDefectDiagnostics(MDD)MemoryDefectDiagnostics前瞻網路安全處理器及相關SOC設計與測試技術研發16Failure/FaultPatternViewer前瞻網路安全處理器及相關SOC設計與測試技術研發17SummaryFault-patternorientedmethodologyfordefectdiagnosticsLayout-baseddefectinjectionanddefectdictionarycreationCombinesstrengthsofconventionalfailure-patternapproachandourfault-typeapproachIntegratedmemoryfailureanalysisframeworkCost-effectivedefectidentificationandyieldimprovementBRAINScreatesBISTcircuitforallmemorycoresUsedinearlystageofSOCdesignMemorylibraryprovideseasyaccesstodifferentmemorytypes

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