DB-SFD64KX32M64P4C-HE-LMC-100B-BC

********************************************************************************TSMCLibrary/IPProduct*Software:TSMCMEMORYCOMPILER2006.03.00*Technology:CE018FE&CE018FF*ProductType:EmbFlashLMC20KCompiler*ProductName:SFD64KX32M64P4C_HE_LMC*Version:100b*GeneratedTime:2011/07/21,08:26:51****************************************************************************************************************************************************************STATEMENTOFUSE**ThisinformationcontainsconfidentialandproprietaryinformationofTSMC.*Nopartofthisinformationmaybereproduced,transmitted,transcribed,*storedinaretrievalsystem,ortranslatedintoanyhumanorcomputer*language,inanyformorbyanymeans,electronic,mechanical,magnetic,*optical,chemical,manual,orotherwise,withoutthepriorwrittenpermission*ofTSMC.Thisinformationwaspreparedforinformationalpurposeandisfor*usebyTSMC'scustomersonly.TSMCreservestherighttomakechangesinthe*informationatanytimeandwithoutnotice.********************************************************************************MemoryName:SFD64KX32M64P4C_HE_LMCMemorySize:65536wordsx32bitsColumnMux:64MemoryArea:X=1823.5400um*Y=1544.6600um===================================================================================TimingWaveforms&scrambletablepleaseseegeneraldatasheetof20KLMCcompiler===================================================================================Documentationnumber:===================1.Test-flowdocument:S-TFL-02-02-082-TSMC0.18UMPURE1.8V20KNON-BLBENDREMBFLASHWAFERLEVELTESTFLOW(L+8)2.Test-modeguide:D-018-FH-02-010-TSMC0.18UM1.8VEMBFLASHTEST-MODEGUIDEFOR20KENDR(Non-BLB,L+8,HECELL)3.20Kqualreportdocument:T-018-CE-QR-027-TSMC0.18UMCOMSEMBEDDEDMEMORYFLASHLOGICBASEDGENERALPURPOSE2P4MSALICIDEAL_FSG1.8&3.3V20KENDRENHANCEDIPQUALIFICATIONREPORT-FAB3GeneralDescription(Notes1-4below):===================TheSFD64KX32M64P4C_HE_LMCisaCMOSpageerase,doubleword(32-bit)programEmbeddedFlashMemorywhichispartitionedintotwomemoryblocks.Oneisthemainmemoryblock,theotheristheinformationblock.Themainmemoryblockisorganizedasa65536wordby32bit.Theinformationblockisorganizedasa512wordby32bit.Theinformationblockcanbeusedforthestorageofdeviceinformation.Thepageeraseoperationerasesalldoublewordswithinapage.Apageiscomposedof4adjacentrowsformainmemoryblockand4adjacentrowsforinformationblock.Thesplitgatecelldesignandthickoxidetunnelinginjectorattainbetterreliabilityandmanufacturabilitycomparedwithalternativeapproaches.TheSFD64KX32M64P4C_HE_LMCerasesandprogramswitha1.8-voltonlypowersupply.Notes:1.Ultra-thicktopmetal4(20KA)processisnotsupportedforthisIP.MemoryFeatures:===============-Single1.8-voltpowersupply-MemoryOrganization65536x32+512x32-PageEraseCapability:1024bytesperpage-Endurance:20,000Cycles(min)with20mseraseand20usprogramtimeat1.8VDD-Greaterthan100yearsDataRetentionunderRoomTemperature-FastPageErase/ByteProgramOperation-AccessTime:18ns(max)-ByteProgramTime:20us(min)-PageEraseTime:20ms(min)-MassEraseTime:20ms(min)-CurrentOperating:17mA(max)Standby:50uA(max)(Tj=-40C~125C)15uA(max)(Tj=-40C~85C)ConnectorDescription:=====================UserMode(Notes1,4)---------ConnectornameDirectionDescription-------------------------------------------------------------------------------XADR[9:0]IXaddressinput,accessrows,XADR[1:0]selectonerowwithinapageofmainmemoryblockorinformationblock.YADR[5:0]IYaddressinput,accessadoublewordwithinarow.DIN[31:0]IDatainputbus.DOUT[31:0]ODataoutputbus.XEIXaddressenable,allrowsaredisabledwhenXE=0.YEIYaddressenable,YMUXisdisabledwhenYE=0.SEISenseamplifierenable.IFRENIInformationblockenable(Notes3)ERASEIDefineserasecycle.MAS1IDefinesmasserasecycle,erasewholeblock.PROGIDefinesprogramcircle.NVSTRIDefinesnon-volatilestorecycle.VDDIPowersupply(Notes2)VSSIGround(Notes2)Notes:1.Needtomultiplexallcontrol,addressanddatasignalstopackagepinstofacilitatedirectmemorytest.2.ThetotalwidthofpowerlineconnectingtoVDD/VSSshouldnotbelessthan30um.3.Whenaccesstheinformationblock,theXADR[9:3]havetobeGND.TheXADR[1:0]areusedtoselectonerowwithinapageintheinformationblock.4.Sincethereadoperationneedserasedreferencecell,customermustperformtheerasereferencecelltestmodeONCEonfreshsample(seewaveformatgeneraldatasheet).TestMode(Notes1,4)---------ConnectornameDirectionDescription---------------------------------------------------------------------------------TMRIRegisterresetfortestmode.Inusermode,itshouldbeconnectedtoVDD.(SeeNotes2)VPPI/OHighvoltagepinusedintestmodeandoperatingin0~13V.AhighvoltagepadwithanI/OpathforVPPpinwillbeprovidedbyTSMC.TM[1:0]I/OAnalogpinsusedintestmodeandoperatingin0~VDD.Theseanalogpinsarehighimpedanceinusermode.TM[0]isstronglyrecommendedtobeaccessibleatwafertest.Inusermode,TM[1]couldbepulledtoGNDorfloating.TM[2]I/OAnalogpinusedintestmodeandoperatingin0~3V.Theanalogpinwithoperationvoltage3Vwasrecommendedtouseforthispin.Inusermode,beingpulledtoGNDorfloatingisstronglyrecommended.Notes:1.Needtomultiplexthetestmoderelatedsignalstopackagepinsformemorytesting.2.TMRisadigitalpinandoperatingin0~VDD.3.TM[2]isusedfordebuggingandwi