xilinx时序约束培训教材

PracticalDesignforXilinx,Section7,12/29/98Page1ConstraintsPracticalDesignforXilinx!!该文的版权归Xilinx公司所有！由收集整理。MakeEDAserveyou!PracticalDesignforXilinx,Section7,12/28/98Page2WhentouseTimingConstraints?ŠConstraintsaddtoruntime,sodon’tusethemunlessyouneedtoŠFasterdesignsneedconstraining—itdependsonthespeedgradeofthedeviceselected,butingeneral,anydesignwithaclockspeedof50MHzorlessandareasonablenumberoflogiclevels(7orless),doesn’tneedtimingconstraints—designsover50MHzshouldusetimingconstraintsŠDesignswithmultipleclockshouldhavetimingconstraints—ifyouhaveasignalclockandareunderthe50MHzlimitabove,youwillnotneedtimingconstraints-youcanalwaysaddthemlaterifyouneedtoŠIfyouhavemulti-cycleclockpaths,youneedconstraints—thesearepathswhereyouknowyouhavetwoormoreclockcyclesforlogictosteady-stateafteraninputchangeŠRuleofThumb:runnon-timingdrivenPARwithoutconstraints,unlessyouarenotreachingyourtiminggoals.—addconstraintssparingly,DONOToverconstrainyourdesign-itwon’thelp,andincreasescanincreaseyourruntimedramatically!!PracticalDesignforXilinx,Section7,12/28/98Page3WhyuseDesignConstraints?ŠConstraintsallowyoutolockyourpinsaftertheboardpinoutisfixed—XilinxM1.5isoftwarehasautomaticpinlocking,andusestheconstraintsfiletopassthesepinlockstofuturerunsofthedesignŠConstraintsallowyoutogiveyourexacttimingrequirementtotheplaceandrouteorfittingsoftware—formanydesigns,theconstraintsarenotneededforplaceandroutetomeettiming-butareanexcellentwaytogetadetailedstatictimingreportwhetherornotyourdesignmeetsyourgoals—formorechallengingdesigns,theconstraintstellthesoftwarewherethecriticalpathsare-andwheretofocustheireffortsŠToknowquicklyifyourdesignmetyourgoals—XilinxhasthebesttiminganalysistoolsintheFPGAindustry—applyingsomesimpleconstraintswillallowyoutogetaquickGO/NO-GOafterplaceandroute.Thesoftwarewilltellyoualltheconstraintsweremet,andyoucanquicklymoveontoboarddebug,withouteverlookingatareport—ifyourconstraintswerenotmet,Xilinxgivesyouthelevelofdetailneededtoquicklyunderstandwhy-andwhereyourdesignneedsmorework.PracticalDesignforXilinx,Section7,12/28/98Page4WhatNeedsConstraining?ŠInternalclockspeedforoneormoreclocksŠI/OspeedŠLogicusingmulti-cycleclocksŠPintopintimingŠPinlocationsandlogiclocationsOUT1XYZ0:92LevelsofLogicI/OSpeedPin2PinSpeedI/OSpeedLogicLocations1LevelofLogicQDQDCLKClk&CESpeedPinLocationsOUT2PinLocationsPracticalDesignforXilinx,Section7,12/28/98Page5TypesofConstraintsSupportedŠTimingConstraints—specifydelayalonglogicpaths—allowsboth“quickanddirty”and“highlydetailed”timingcontrolŠLocationConstraints—specifylocationofcomponentsonFPGA—specifymappingconstraintsINSTMY_FMAPBLKNM=ABCINSTFLOP1BLKNM=ABCINSTFLOP2BLKNM=ABCPracticalDesignforXilinx,Section7,12/28/98Page6WheredoConstraintsgo?ŠTimingconstraintsmaybeappliedtoaschematicusingthetimespecsymbol(FROM:TO’s)ŠTheycanbeaddedtoHDLsourcecodeifyourcompilersupportsthemŠTheycanbeinputinaseparatefilecalleda.UCF(userconstraintsfile),orasynthesizergenerated.NCF(netlistconstraintsfile)ŠSomeconstraintsmustbeplacedinthePCF(physicalconstraintsfile).Normally,thePCFshouldbeavoidedbyusers.TIMESPECPracticalDesignforXilinx,Section7,12/28/98Page7HowdoICreateConstraints?ŠWritethembyhandusingtheXilinxLibrariesGuideasasyntaxguide—thisisthemostdifficultmethod,butprovidesthemostcontrolŠEnterthemwithyourHDLorschematic,andpassthemthroughwiththenetlist—thisisamucheasiermethod—ithaslimitedcontroloverthenamingofconstraints-insomecasescanoverconstrainthedesign—additionally,youneedtolearntwoconstraintlanguages-thesynthesizer’sandeventuallyXilinx’sŠUsetheXilinxGraphicConstraintsEditor—providestheeasiestpathtoenteringmostconstraints—exportsstandardXilinxConstraintsSyntax—givescompletecontroloverthedesign—insomecase,someadvancedconstraintsarenotyetsupported,liketemperatureorvoltageforexamplePracticalDesignforXilinx,Section7,12/28/98Page8ConstraintsEditorŠRemovestheneedtoknowconstraintsyntaxŠDoesnotremovetheneedtoknowthedesignŠCreatesXilinxtimeandplacementconstraintsŠFivetabsusedforconstraining:—GlobalConstraints:PERIOD,OFFSETINBEFORE,OFFSETOUTAFTER,PadtoPad—PortConstraints:PinLocations,OFFSETINBEFORE,OFFSETOUTAFTER,FAST/SLOW,PinProhibits—AdvancedConstraints:TIMEGRP,TPTHRU,GroupOFFSETINBEFORE,GroupOFFSETOUTAFTER,FROM:TO,FROM:TO:TIG,NETTIG—EditableConstraints:Listgroupsandconstraintscreated.Disablingordeletionofconstraints.—SourceConstraints:ReadOnly.Constraintfrom.ngdfile.Constraintscanbeoverridden,butnotremoved.PracticalDesignforXilinx,Section7,12/28/98Page9BriefReviewofConstraintFlowPHYSICALDOMAINUsernetlistandexistingconstraintsPARTRCEEPICNGDANNODRCXNF/EDIFnetlistConstraintEditorUCFNGDBUILDMAP.PCF.NCDConstraintsEditorNGDBUILDDesign_name.ngdXNF/EDIFnetlistExistingUCFUserConstraintsFileLOGICALDOMAINDESIGNTRANSLATIONMappeddesignandphysicalconstraintsPracticalDesignforXilinx,Section7,12/29/98Page10TimingConstraints(I)UsingConstraintEditortocreatePERIODandOFFSETconstraintsPracticalDesignforXilinx,Section7,12/28/98Page11GlobalTABPeriod,PadtoSetup,andClockToPad,PadtoPadwillbeautomaticallyfilledinbyCEfromyourUCFpe