Synopsys-IC-Complier设计流程指导书-Basic-Flow

11-Agenda©2007Synopsys,Inc.AllRightsReservedSynopsys20-I-071-SSG-007DAY1Introduction&OverviewiICCompilerBasicFlow1Placement,Power&Test221-UnitObjectivesAftercompletingthisunit,youshouldbeableto:CreateaMilkywaylibrarytoholdyourdesignReadallnecessaryfilesrequiredtorunICCompiler,resolvingcommonerrors/warningsSetuptimingforanalysisandoptimizationsExecutethebasicflowforplacement,CTSandroutinginICCompiler31-UnitRoadmapDataSetupReadnetlistandSDCSetuptiminglibrariesSetupMilkywayApplythefloorplanBasicFlowPlacementClocktreesynthesisRoutingAnalysisTimingSetupandRCModelingTimingvariablesRCandTLU+modelsDelaycalculationBreak41-GeneralICCompilerFlowSynthesisUnit1Unit2Unit3Unit6Unit7Unit5DesignSetupDesignPlanningplace_optclock_optroute_optChipFinishing51-Placement,CTS,RoutingwithOptimizationsPlaced,Routed&OptimizedDesignwithClockTreesGate-LevelNetlistOptional:FloorplanIPICCompiler61-1.TechFile2.TLU+3.IOTDFfile4.Netlist5.SDC1.IOpadsplaced2.Chip/coreboundary3.Cellrows,wiretrackscreated4.MacroplacementfinalOutputplace_optclock_optroute_optChipfinishingandDFMPowerplan1.Stdcellsplaced2.Clocktree(s)built3.ClockandsignalroutingcompletedOutputFloorplanICCompilerDataFlowDEFMWDesignPlanning71-UnitFlow:FromSetuptoOutputLogicalDataSetupPhysicalDataSetupplace_optclock_optroute_optAnalysisOutput81-LogicalDataGate-LevelNetlist(s)LogicalLibraries.dblinkcheck_timingcreate_clock–period10...set_input_delay–max1.2...set_output_delay–max2.5...set_driving_cell.........Logical(Timing)ConstraintsLogicalDataPhysicalDataplace_optclock_optroute_optAnalysisOutputLogicalData91-ReadingGate-LevelNetlistsfromSynthesisICCompilercanopenaMilkywaydatabasewrittenbyDesignCompilerAndotherformatssupportedbyDesignCompilerYoucanreadoneormanyfilesread_ddcread_verilogread_vhdl…read_verilogfile1.vfile2.v…MilkywayandDDCcanalsocontaindesignattributes!101-MY_TOP_DESIGNNoMultiplyInstantiatedDesignsICCompilerdoesnotsupportnon-uniquifieddesigns,i.e.designswithmultipleinstantiations!Whenreadinginanon-uniquifieddesign,thefirstcommandsofyourICCscriptshouldbe:current_designMY_TOP_DESIGNuniquifyPARSERPARSER1PARSER2PARSER3111-LogicalLibrariesProvidetimingandfunctionalityinformationforallstandardcells(and,or,flipflop,…)Providetiminginformationforhardmacros(IP,ROM,RAM,…)Definedrive/loaddesignrules:MaxfanoutandtransitionMax/MincapacitanceSpecifiedasfollows:LogicalLibraries.dbsetlink_library*gates.dbio.dbrams.db“*”=SearchalldesignsinmemoryMakesurethefirstspecifieddbcontainsthecorrectunits!121-CCSLibrarySupportICCompilersupportsNLDMandCCS(CompositeCurrentSource)librariesCurrent-basedapproachmoreaccuratelymodelsTiming,Noise,PowerHighimpedanceinterconnectMillereffectDynamicIR-dropMulti-voltageTemperatureInversionNLDMsarenotaccurateenoughfor90nmandbelowUseCCS131-CCSSupportedThroughoutGalaxyToolsTimingNoisePowerNanoCharPrimeTimeICCompilerDesignCompilern/aCCSSupportMilkywaySignoffDesignCompilerICCompilerGalaxy141-HowdoesICCompilerFindFiles?Bydefault,youmustspecifytheunix-pathforallfiles(relativeorabsolute)Youmayspecifywheretolookforfiles:TheabovepathswillbeusedbyICCompilerforreadingoraccessingfileslappendsearch_path./design_data../scriptslappendsearch_path[glob$MW_libs/*/LM]151-TargetLibrariesAlongwiththelink_libraryandsearch_pathvariables,youneedtospecifythelogicallibrarythatwillbeusedformapping/optimization:Typically,thetarget_librarypointstoyourstandardcellsonlysettarget_librarygates.db161-*ResolvingReferencesGate-levelnetlistscontainreferencestostandardcellsandmacros,whicharestoredinthelogicallibraries,aswellasotherhierarchicallogicblocksThelinkcommandwillensurethatallreferencescanberesolvedlinkrisc_corenandnorinvffsdram_ifGate-LevelNetlist(s)mem.dbgates.dbip.dbpci_corelink_library171-Shortcuts…import_designsorca.v\-formatverilog\-topORCA_TOPReplaces:read_verilog–netlistorca.vcurrent_designORCA_TOPuniquifylinksave_mw_cel–asORCA_TOPFormatcanbeverilog,db,ddc181-TimingConstraints“TimingConstraints”arerequiredtocommunicatethedesign’stimingintentionstoICCompilerTheyshouldbethesameonesusedforsynthesiswithDesignCompiler(preferablySDC)create_clock–period10[get_portsclk]set_input_delay4–clockclk\[get_portssd_DQ[*]]set_output_delay5–clockclk[get_portssd_LD]set_load0.2[get_portspdevsel_n]set_driving_cell–lib_cellbuf5\[get_portspdevsel_n]...read_sdctiming_constraints.sdcSDC=SynopsysDesignConstraints191-ConstraintManagement2006.06andlaterremove_sdc•RemovesallSDCconstraintsremove_ideal_network-all•Removesideal_networkattributes,latenciesandtransitionsremove_annotations•Removesallannotateddelays,transition,resistance,capacitance,checksToremoveallsettings:reset_design•Removesalloptimizationattributes(dont_touch,size_only…)andallconstraints.201-TimingCheckBeforeproceeding,youshouldensurethatthedesigniscompletelyconstrainedICCompilerwillnotoptimizepathsthatarenotconstrainedfortimingNocheckingformissingexternalloadsordrivecharacteristicswillbeperformed!check_timing!211-check_timingreportsallunconstrainedpathsFalsepathsarealsoconsideredunconstrained!Toverifythatunc